The present invention relates generally to latches, and more specifically to level converting latches in dual-supply voltage designs.
Latch circuits are widely used to temporarily store data and transfer the data from one part of a circuit to another part of the circuit. Integrated circuits such as microprocessors and memory devices often include a number of latch circuits and typically have a single supply voltage. However, because of demand for longer battery life in ultra low-power microprocessors and other circuits, designers have proposed a concept of dual-supply voltages. This concept allows critical units of the integrated circuits to operate at a higher supply voltage (Vcch) while non-critical units operate at a lower supply voltage (Vccl). When circuits operate at a lower voltage (Vccl), they operate slower but consume less power.
A problem arises when a unit operating at Vccl interfaces with a unit operating at Vcch. To solve this problem, level converting latches have been suggested. FIG. 1 shows a prior art level converting latch 100. Latch 100 receives a low swing signal or xe2x80x9cVccl signal,xe2x80x9d Din, and outputs a high swing signal or xe2x80x9cVcch signal,xe2x80x9d Dout. A Vccl signal has high potential level corresponding to Vccl; a Vcch signal has a high potential level corresponding to Vcch, which is greater than Vccl. Both Vccl and Vcch have the same low potential level, e.g., zero or ground. Latch 100 includes internal nodes A and B. Transistors N1 and N2 connect to nodes A and B and to transistor N3 and inverter I1 to allow node A or B to discharge to ground, in response to a potential level of a clock signal CLK. Cross-coupled inverters I2 and I3 connect to node A and B to operate as a conversion and a feedback circuit.
When the CLK signal switches from zero to Vcch, transistor N3 turns on. Depending on the level of the Din signal, either node A or B selectively discharges to ground through transistors N1 and N3 or N2 and N3. Inverters I2 and I3 convert the Vccl Din signal to a Vcch signal and hold it as potential levels at nodes A and B. Inverter I4 drives the Vcch signal to an output of the latch as the Dout signal. As long as the CLK signal is at Vcch, latch 100 is transparent and the Vccl Din signal is available at an output of latch 100 as the Vcch Dout signal.
When the CLK signal switches from Vcch to zero, transistor N3 turns off, stopping the effect of the Din signal on nodes A and B. However, inverters I2 and I3 hold nodes A and B at the previous potential level of the Din signal until the CLK signal switches to Vcch.
A problem arises when node A or B discharges to ground but nodes A or B hold an opposite potential level from the previous cycle. For example, when the CLK signal switches from zero to Vcch, transistor N3 turns on and node A discharges to ground. However, if node A holds the Vcch potential, discharging to ground would cause a charge contention, leading to poor performance.
Further, since node A or B discharges to ground through a number of transistors, either N1 and N3 or N2 and N3, latch 100 may introduce unnecessary delay between the Din signal and the Dout signal.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for an improved level converting latch.